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clo c k distribution - s m t 1 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz functional diagram general description t he 1-to-9 fanout buffer is designed for low noise clock distribution. i t is intended to generate relatively square wave outputs with rise/fall times < 100 ps. t he low skew and jitter outputs of the, combined with its fast rise/fall times, leads to controllable low-noise switching of downstream circuits such as mixers, adcs/dacs or s e r de s devices. t he noise foor is particularly important in these applications, when the clock-network bandwidth is wide enough to allow square-wave switching. driven at 2 ghz, outputs of the have a noise foor of -166 d b c/hz, corresponding to a jitter density of 0.6 asec/rthz - or 50 fs over an 8 ghz bandwidth. t he input stage can be driven single-ended or differentially, in a variety of signal formats (cm l , l vd s , l vpec l or cm os ), ac or dc coupled. t he input stage also features adjustable input impedance. i t has 8 l vpec l outputs, and 1 cm l output with adjustable swing/power-level in 3 d b steps. i ndividual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface. features u ltra l ow n oise floor: -166 d b c/hz @ 2 ghz wideband: dc - 8 ghz o perating frequency flexible i nput i nterface: l vpec l , l vd s , cm l , cm os compatible ac or dc coupling o n-chip t ermination 50 or 150 ? (100/300 ? diff.) multiple o utput drivers: u p to 8 differential or 16 s ingle-ended l vpec l o utputs: 800 mvpp into 50 ? s ingle-ended (+3 d b m fo) o ne adjustable power cm l / r f o utput: -9 to 3 d b m s ingle-ended s erial or parallel control, hardware chip-enable power-down current < 1 ua 32 l ead 5x5 mm s m t package 25 mm 2 typical applications t he is suitable for: ? sonet , fibre channel, gige clock distribution ? adc/dac clock distribution ? l ow s kew and jitter clock or data fanout ? wireless/wired communications ? l evel t ranslation ? high performance i nstrumentation ? medical imaging ? s ingle-ended to differential conversion for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 2 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz table 1. electrical specifcations u nless otherwise specifed: t = 27 c, r egulated vdd of 3.3 v, 2 ghz, 6 d b m in, ac coupled single ended input and output, 120 ?/leg dc termination, ac coupled into 50 ? measuring load. effects of customer eval board ( evaluation pc b s chematic ) are de-embedded. for convenience, all voltages are referenced to g n d (0v), but negative supply references are acceptable. parameter conditions min. t y p. max. units dc i nput characteristics vdd (vcchf=vcca=vcc b =vcc r f) 3.0 3.3 3.6 v i nput common mode voltage 1.35 2 vdd - 0.2 v i nput s wing ( s ingle ended) 0.2 2 vpp i nput capacitance 0.5 pf i nput i mpedance s ingle-ended s electable 50 / 150 ? differential s electable 100 / 300 ? i nput b ias current b ase current under external dc bias, i nternal termination open. 165 a l ogic i nputs s witching t hreshold (vsw) v i h/v il within 50 mv of vsw 38 47 54 %vdd l vpec l dc o utput characteristics o utput voltage high l evel @ 3.3 v = 2.25 vdd - 1.2 vdd - 1.0 vdd - 0.8 v o uput voltage common mode @ 3.3 v = 1.82 vdd - 1.7 vdd - 1.5 vdd - 1.3 v o utput voltage l ow l evel @ 3.3 v = 1.42 vdd - 2.1 vdd - 1.9 vdd - 1.7 v o utput voltage, s ingle-ended 800 mvpp ac performance i nput/ o utput frequency [1] > 400 vpp single-ended dc 8000 mhz 3 d b b andwidth 4000 mhz o utput r ise/fall t ime 20% to 80% 65 ps t ypical channel s kew across all l vpec l outputs relative to channel 1 0 1.5 3.1 ps s mall s ignal gain s 21 1000 mhz 26 db 4000 mhz 15 db i nput p1d b 1000 mhz -20 d bm 4000 mhz -10 d bm s aturated power in fundamental tone ( s ingle-ended) 1000 mhz 2.5 d bm 4000 mhz -0.5 d bm o utput voltage s wing (vppd into 100 ?) 700 mhz 1.5 1.6 1.7 v 2000 mhz 1.2 1.3 1.4 v [1] for frequencies < 700 mhz, square wave signals should be used to maintain high quality phase noise performance. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 3 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz parameter conditions min. t y p. max. units 4000 mhz 1.1 1.2 1.3 v harmonics fo 2 d bm 2fo -25 db c 3fo -8 db c 4fo -28 db c 5fo -12 db c ssb phase n oise at 100 hz o ffset 622.08 mhz carrier frequency -147 d b c/hz 1750 mhz carrier frequency -147 d b c/hz 4000 mhz carrier frequency -147 d b c/hz ssb phase n oise floor [2] 100 mhz carrier frequency -167 d b c/hz 622.08 mhz carrier frequency -167 d b c/hz 1750 mhz carrier frequency -166 d b c/hz 2000 mhz carrier frequency -166 d b c/hz 4000 mhz carrier frequency -163 d b c/hz 4200 mhz carrier frequency -162 d b c/hz floor jitter density 622.08 mhz carrier frequency 1.8 asec/hz 1750 mhz carrier frequency 0.7 asec/hz 4000 mhz carrier frequency 0.5 asec/hz i ntegrated r m s jitter 622.08 mhz carrier frequency 100 hz to 100 mhz 17 fs rms 12 khz to 20 mhz 8 fs rms 20 khz to 80 mhz 17 fs rms 50 khz to 80 mhz 17 fs rms 4 mhz to 80 mhz 16 fs rms 1750 mhz carrier frequency 100 hz to 100 mhz 7 fs rms 12 khz to 20 mhz 3 fs rms 20 khz to 80 mhz 6 fs rms 50 khz to 80 mhz 6 fs rms 4 mhz to 80 mhz 6 fs rms 4000 mhz carrier frequency 100 hz to 100 mhz 4 fs rms 12 khz to 20 mhz 2 fs rms 20 khz to 80 mhz 4 fs rms 50 khz to 80 mhz 4 fs rms 4 mhz to 80 mhz 4 fs rms o utput r eturn l oss 500 mhz to 4 ghz -16 -12 -8 db table 1. electrical specifcations (continued...) [2] cm l buffer has similar phase noise characteristics at maximum output power level. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 4 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz parameter conditions min. t y p. max. units i solation i n to o ut - chip disabled 47 db o ff isolation - r elative to power of neighboring driven port 700 mhz 60 48 db 4000 mhz 50 32 db o utput to o utput i solation with 500 mhz aggressor s ignal i njected into o utput port t o l ocally paired output buffer 25 db t o other buffers 45 db r f o utput b uffer 3 d b b andwidth 5000 mhz max o utput power (vs t emperature at 2 ghz) s ingle-ended 3 3.2 d bm power control r ange (3 d b steps) s ingle-ended -9 3 d bm delay r elative to l vpec l o utput -140 ps power s upply r ejection fm/phase pushing 0.8 ps/v am r ejection 7 db current consumption (3.3 v u nloaded o utputs) chip disabled 1 a 1 o utput 60 ma 2 o utputs 71 ma 3 o utputs 97 ma 4 o utputs 108 ma 5 o utputs 134 ma 6 o utputs 144 ma 7 o utputs 170 ma 8 o utputs 180 ma 8 + r f b uffer (min to max power) 198 234 ma table 1. electrical specifcations (continued...) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 5 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz typical performance characteristics u nless otherwise specifed: t = 27 c, r egulated vdd = 3.3 v, 2 ghz, 6 d b m in, ac coupled single ended input and output, 120 ?/leg dc termination, ac coupled into 50 ? measuring load. figure 1. lvpecl output vs. frequency [1] figure 2. lvpecl output vs. frequency [1] figure 3. current consumption vs. num. of enabled buffers & load resistors [2] figure 4. skew of lvpecl outputs relative to output channel 1 [4] [1] +2d b m input, u ncorrected for board loss. measurement is band limited by the trace bandwidth of 7 ghz. [2] b uffers 1 through 8 are successively turned on. r f min - r f buffer turned on with minimum gain, r f max - r f buffer turned on with maximum gain [3] 200 ? t ermination, corrected for board loss. [4] characterized at 2 ghz, effects of customer evaluation board skew and loss are embedded. [5] t he graph shows only output trace distortion. -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -800 -600 -400 -200 0 200 400 600 800 time (picoseconds) output voltage (v) 4 ghz outp 4 ghz outn 2 ghz outn 1 ghz outp 1 ghz outn 2 ghz outp -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0 20 40 60 80 100 120 4 ghz 2 ghz 1 ghz amplitude (v differential) time (ps) figure 5. fundamental output power vs. input power [3] -20 -15 -10 -5 0 5 -30 -24 -18 -12 -6 0 6 input power (dbm) output power (dbm) 400 mhz 2 ghz 3 ghz 4 ghz 5 ghz 6 ghz figure 6. evaluation board lvpecl output trace loss vs. frequency [5] -15 -10 -5 0 5 10 15 p1 p2 p3 p4 p5 p6 p7 p8 relative delay (psec) output channel 0 100 200 300 400 500 1 2 3 4 5 5 6 7 8 rf min rf max current (ma) number of outputs successively turned on ground current (does not depend on termination) 120 ohm dc termination 300 ohm dc termination 200 ohm dc termination -7 -6 -5 -4 -3 -2 -1 0 100 1000 10000 output trace loss (db) output frequency (mhz) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 6 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz figure 7. rf buffer fo output power vs. frequency & temperature (max gain) figure 8. rf output power control figure 9. fundamental output power vs. frequency & temperature [6] [6] measured single-ended. corrected for trace loss. 200 ? dc termination, 3.3 v +6 d b m single-ended input. hmc987 l p5e ac coupled to 50 ? instrument. [7] i nput signal power = + 6 d b m. 120 ?/leg dc termination. ac coupled via 50 pf to 26 ghz o scilloscope (50 o hm/leg termination). figure 10. fundamental output power vs. frequency & supply voltage at 27 c [6] figure 11. fundamental output power vs. frequency & termination at 27 c [6] figure 12. signal swing vs. frequency [7] -3 -2 -1 0 1 2 3 4 100 1000 10000 -40 c 27 c 85 c output power (dbm) output frequency (mhz) -3 -2 -1 0 1 2 3 4 100 1000 10000 output power (dbm) output frequency (mhz) 3.0 v 3.2 v 3.3 v 3.5 v 3.6 v -3 -2 -1 0 1 2 3 100 1000 10000 120 ohms 200 ohms 300 ohms output power (dbm) output frequency (mhz) -3 -2 -1 0 1 2 3 4 100 1000 10000 -40 c 27 c 85 c output power (dbm) frequency (mhz) -12 -9 -6 -3 0 3 6 100 1000 10000 output power (dbm) frequency (mhz) reg04h[2:0] = 1d reg04h[2:0] = 2d reg04h[2:0] = 3d reg04h[2:0] = 4d reg04h[2:0]= 5d 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 1000 2000 3000 4000 5000 6000 7000 8000 signal swing (vppd) frequency (mhz) corrected for evaluation board loss observed and not corrected for evaluation board loss for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 7 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz -260 -258 -256 -254 -252 -250 -248 0 500 1000 1500 2000 fom (dbc/hz) sinusoidal input frequency (mhz) -180 -170 -160 -150 -140 -130 -120 -110 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) frequency offset (hz) hmc830lp6ge used as source source + fanout output noise -170 -168 -166 -164 -162 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 phase noise (dbc/hz) vdd 300 ohm termination 120 ohm termination 200 ohm termination figure 13. phase noise performance at 2 ghz (differential drive) [9] -170 -168 -166 -164 -162 -160 -50 0 50 100 phase noise (dbc/hz) temperature (deg. c) frequency = 100 mhz frequency = 2 ghz frequency = 4.2 ghz figure 14. phase noise floor vs. slew rate -168 -166 -164 -162 -160 -158 -156 -15 -10 -5 0 5 10 phase noise (dbc/hz) input power (dbm) [8] i nput power = 10 d b m single-ended. phase n oise floor (d b c/hz) = f o m (d b c/hz)) + 10log(fout [hz]) [9] hmc830 l p6ge used as signal source, driving +9 d b m differentially. figure 15. phase noise floor at 1.6 ghz vs. input power figure 16. phase noise performance with low frequency sinusoidal inputs [8] figure 17. phase noise floor at 2 ghz vs. vdd and dc termination figure 18. phase noise floor vs. temperature -169 -168 -167 -166 -165 -164 -163 -162 -161 024681012 phase noi se (dbc/hz) slew rate (v/nsec) pin = 10 dbm pin = 0 dbm pin = 10 dbm pin = 0 dbm 2 ghz 4 ghz 100 mhz pin = -3 dbm pin = 3 dbm for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 8 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz figure 19. harmonic performance (single-ended input & output) [10] -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 power (dbm) frequency (mhz) fo 2fo 3f0 4fo 3fo 5fo [10] n ot corrected for board/cable loss. [11] effects of the customer evaluation board are not corrected. i mprovements in s 11 and s 22 are possible under different evaluation board confgurations figure 20. s-parameters - s11 [11] -30 -25 -20 -15 -10 -5 0 0 2000 4000 6000 8000 10000 s11 (db) frequency (mhz) single-ended differential figure 21. s-parameters - s12 [11] figure 22. s-parameters - s22 [11] -110 -100 -90 -80 -70 -60 -50 -40 -30 0 2000 4000 6000 8000 10000 s12 (db) frequency (mhz) single-ended differential -30 -25 -20 -15 -10 -5 0 0 2000 4000 6000 8000 10000 s22 (db) frequency (mhz) differential single-ended for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 9 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz table 2. pin descriptions pin n umber function description 1 vcchf power s upply 2 c lk p differential clock inputs 3 c lkn 4 s di s erial port data input 5 s d o s erial port data output 6 pm o de- se l parallel mode select. i f 1, pins ( s c lk , s d i , s e n ) are interpreted as a control-word which enables different buffers. s ee section parallel port control 7 r f out p differential signal output 8 rf outn 9 vcc rf power supply 10 sc lk s erial port clock 11 s en s erial port latch enable 12 out p8 differential signal output 13 outn 8 14 out p7 differential signal output 15 outn 7 16 vcc b power supply 17 outn 6 differential signal output 18 out p6 19 outn 5 differential signal output 20 out p5 21 out p4 differential signal output 22 outn 4 23 out p3 differential signal output 24 outn 3 25 vcca power supply 26 outn 2 differential signal output 27 out p2 28 outn 1 differential signal output 29 out p1 30 rf bu fe n active high r f buffer enable. t he polarity of this control input can be swapped via s p i bit r eg03h [4]. 31 ce n hardware chip enable 32 nc n o connect for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 10 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz table 3. absolute maximum ratings parameter r ating max vdc to paddle on supply pins 1, 9, 16, 25 -0.3 v to +4 v max r f power c lk p, c lkn 15 d b m single-ended c lk p, c lkn - 0.3 v to 3.6 v l vpec l min o utput l oad r esistor 100 o hms to g n d l vpec l o utput l oad current 40 ma/leg digital l oad 1 k? min digital i nput voltage r ange -0.3 to 3.6 v t hermal r esistance (junction to ground paddle) 25 0 c/w o perating t emperature r ange -40 o c to +85 o c s torage t emperature r ange -65 o c to + 125 o c maximum junction t emperature +125 o c r efow s oldering peak t emperature 260 o c t ime at peak t emperature 40 sec e s d s ensitivity h b m class 1 b s tresses above those listed under absolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 11 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz outline drawing not e s : [1] pac k age bo dy ma t e ri a l : lo w str e ss in jec tion m ol ded p l a sti c sili ca a n d sili c on i mp r eg n a t ed. [2] l ead a n d g roun d padd l e ma t e ri a l : c o ppe r a llo y. [3] l ead a n d g roun d padd l e p l a tin g: 100% ma tt e tin . [4] d i me nsions a r e in in che s [m illi me t e rs ]. [5] l ead s pac in g tol er a n ce is non -c u m ul a ti ve. [6] pad burr l e n g t h s ha ll b e 0.15 mm max. pad burr he i gh t s ha ll b e 0.05 mm max. [7] pac k age wa r p s ha ll not exceed 0.05 mm [8] a ll g roun d l ead s a n d g roun d padd l e m ust b e sol de r ed to pc b r f g roun d. [9] r efe r to h ittit e app li ca tion not e f or su gge st ed pc b l a n d pa tt e rn . table 4. package information part n umber package b ody material l ead finish m sl r ating package marking [1] r oh s -compliant l ow s tress i njection molded plastic 100% matte s n m sl 1 [2] h987 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 12 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz evaluation pcb t he circuit board used in the application should use r f circuit design techniques. s ignal lines should have 50 o hms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. t he evaluation circuit board shown is available from hittite upon request. table 5. evaluation order information i tem contents part n umber evaluation pc b evaluation pc b eva l 01- evaluation k it evaluation pc b usb i nterface b oard 6 usb a male to usb b female cable cd ro m (contains u ser manual, evaluation pc b s chematic, evaluation s oftware, e kit 01- for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 13 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz evaluation pcb schematic c114 depop c113 depop c112 depop c111 depop c110 depop c109 depop c108 depop c6 4.7uf vcchf j7 1 2 130-00080-00 sch, eval customer 11/18/2010 b 1 1 d.young hmc987lp5e a cp110719 ----- production release cp110719 v.vaduva 05/25/11 06/23/11 d. aceval changer32,r35,r36,r63,r38,r39,r41,r42,r44,r45,r47,r48,r49,r50,r51,r52,r53,r54,r56,r57cp110885 cp110885 b 29-06-2011_13:34 ---- 20 alpha rd chelmsford, ma 01824 hittite microwave corporation a b notice of proprietary property: this document and the information contained in it are the proprietary property of hittite microwave corporation. it may not be copied or used in any manner nor may any of the information in or upon it be used for any purpose without the expressed written consent of an authorized agent of hittite microwave corporation. a b 4 3 2 1 of 3 2 1 drawn by date code id no. size rev 1cn88 revisions title drawing #: project c sheet rev ecn# zone name date description c c d d 5 6 5 6 4 nc nc nc c21 0.1uf j30 ssw-106-01-t-d 9 11 1 3 5 7 2 4 6 8 10 12 tp2 tp1 j11 1 2 vccb vcca vccrf j26 j19 j14 j1 j2 j25 c22 0.1uf j23 j29 j27 j24 j22 c17 depop c31 depop c32 depop c39 depop c49 depop j20 c20 depop c52 depop c42 depop c74 depop c93 depop c65 depop c61 depop c75 depop c66 depop c87 depop c76 depop c23 depop c33 depop c24 depop c34 depop c26 depop c36 depop c95 depop c73 depop c72 depop c71 depop c80 depop c82 depop c90 depop c91 depop c60 depop c64 depop c63 depop c70 depop c68 depop c78 depop c43 depop c44 depop c46 depop c58 depop c56 depop c55 depop r33 depop r34 depop j12 j28 j21 j17 j18 j15 j13 j3 j4 r31 depop j5 1 2 j6 1 2 j8 1 2 j10 1 2 c4 0.1uf vccb vcca vccrf c101 100pf vcchf c54 0.1uf c102 100pf c53 0.1uf c100 100pf c5 100pf c3 4.7uf j9 1 2 r5 200k r6 200k r8 200k r9 200k r10 200k r7 200k r2 200k vccrf nc u1 hmc976lp3e 1 2 3 4 15 12 11 10 9 13 16 14 5 6 7 8 hv vr vdd vrx ref rd en band gap 400 nc nc nc nc nc nc nc nc nc c1 0.1uf c2 4.7uf hmc987lp5e u2 24 6 1 9 8 7 25 16 2 32 31 30 29 28 27 26 5 4 3 17 18 19 20 21 22 23 10 11 12 13 14 15 outn7 outp7 outn8 outp8 sen sclk outp3 outn4 outp4 outp5 outn5 outp6 outn6 clkn sdi sdo outn2 outp2 outn1 outp1 rfbufen cen clkp vccb vcca rfoutp rfoutn vccrf vcchf pmode_sel outn3 spi nc c106 depop c105 depop r63 1k 0 r4 0 r1 c10 100pf c12 100pf r11 0 r13 0 r14 0 depop r32 r12 0 depop r35 depop r36 r41 200 c83 depop c84 depop c18 100pf c16 100pf c28 100pf c48 100pf c50 100pf c40 100pf r47 200 c41 depop c51 depop c38 100pf c79 100pf c62 100pf c69 100pf c88 100pf c81 100pf c92 100pf c98 100pf c99 100pf c96 100pf c94 100pf r53 200 c85 100pf c86 100pf c67 100pf c97 100pf r50 200 c77 100pf c47 100pf c59 100pf c37 100pf c27 100pf nc c7 0.1uf r62 0 c104 depop c103 depop c89 100pf c9 depop c13 depop c8 depop c11 depop r25 0 r61 depop r3 82k r17 0 r16 0 r15 0 r21 0 r23 0 r24 0 r26 0 r29 0 r30 0 r20 0 r19 0 r18 0 r22 0 c25 100pf c35 100pf c14 100pf c15 100pf c57 100pf c45 100pf r39 200 r40 0 r42 200 r48 200 r45 200 r46 0 nc c29 depop r44 200 r43 0 r55 0 r49 200 r51 200 r59 0 r52 200 r56 200 r57 200 r54 200 r58 0 r27 0 r28 0 r60 0 j16 r38 200 r37 0 c19 depop c30 100pf c107 depop sdo sen cen rfbuf_en pmod_sel sdi sck header to usb board out5-p out5-n out6-p out6-n out7-n out7-p out8-n out8-p out2-p out2-n out1-n out1-p clk-n clk-p gnd +5v max 350ma 3.3v rfout-p rfout-n out3-p out3-n out4-n out4-p for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 14 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz theory of operation parallel port control t he various outputs of the can be enabled/disabled by using parallel pin control, or via the s p i . i n parallel-mode (pm o de- s e l = 1), the s p i input pins ( s c lk , ski , s e n ) are re-interpreted as a 3-bit control bus, and enable the l vpec l drivers according to the following truth table. s c lk , s d i , s e n 000: out 2 001: out 2 + out 7 010: out 2 + out 7 + out 4 011: out 2 + out 7 + out 4 + out 6 100: out 2 + out 7 + out 4 + out 6 + out 5 101: out 2 + out 7 + out 4 + out 6 + out 5 + out 3 110: out 2 + out 7 + out 4 + out 6 + out 5 + out 3 + out 8 111: out 2 + out 7 + out 4 + out 6 + out 5 + out 3 + out 8 + out 1 u nder s p i control (pm o de- s e l = 0, see section r egister map for the register map and s p i protocol details), there is slightly more fexibility in that any combination of buffers can be enabled or disabled via the individual buffer enable bits in r eg02h . t he part features switches on both the input and output signals, so that when the part is disabled (via either the ce n pin, or the s p i control bit [0]), the power-down current drops to < 2 a, regardless of the io termination scheme. input stage t he input stage, figure 38 , is fexible. i t can be driven single-ended or differential, with l vpec l , l vd s , or cm l signals. i f driven single-ended, a large ac coupling cap to ground should be used on the undriven input. t he input impedance is selectable, via parallel port control [3], between 50 ? or 150 ? (100 ? or 300 ? differential). t he dc bias level of 2.0 v can be generated internally by programming parallel port control [1] =1 (default confguration), supplied externally, or generated via an l vpec l termination network inside the part. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 15 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz figure 26. input stage [4] to figure 28 illustrate common input interface confgurations. figure 27. dc coupled cml interface figure 28. dc coupled cmos interface for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 16 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz figure 29. dc coupled lvpecl interface figure 30. ac coupled differential cml / lvpecl / lvds / cmos interface figure 31. ac coupled single-ended cml / lvpecl / lvds / cmos interface lvpecl output stage t he l vpec l output driver produces up to 1.6 vppd swing into 50 ? loads. l vpec l drivers are terminated with off-chip resistors that provide the dc current through the emitter-follower output stage. t he output stage has a switch which disconnects the output driver from the load when not used. t he switch series resistor signifcantly improves the output match when driving into 50 ? transmission lines. t he switch series resistor causes a small dc level shift and swing degradation, depending on the termination current. i f unused, disabled l vpec l outputs can be left foating, terminated, or grounded. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 17 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz figure 32. output stage figure 30 to [8] illustrate common output interface confgurations. figure 33. dc coupled to lvpecl interface figure 34. ac coupled to lvds / cml / lvpecl / cmos for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 18 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz figure 35. dc coupled to cmos interface t he user has a number of choices in how they connect l vpec l drivers and receivers, and there are great number of resources that deal in detail with this issue. as a quick introduction, there are compromises between matching performance, common mode levels, and signal swing. for clocking applications, the user often has the luxury of using ac coupling, unlike in many data-path situations. figure 36 shows a simplifed interface schematic between an l vpec l output and input stage - where various options and trade-offs for the termination components are provided in t able 6 . t he hittite evaluation board has a great deal of fexibility in how the i / o s are confgured, and allows the confguration in figure 33 , among many others. figure 36. recommended interface diagram table 6. interface values r s - u sed to increase r o to match to 50 ? environment. already has ~ 10 ? internally. 0 ? hittite ev b : l argest signal swing, lowest common mode shift 10 ? b etter s 22 r l - dc current termination for l vpec l output stage 120 ? hittite ev b default: s tandard l vpec l termination voltages 200 ? r educed current, no performance degradation 300 ? further reduced current, lower output power but fatter frequency response o pe n i f using internal dc termination network at the r x cac - ac coupling cap bi g cap hittite ev b default: i f using ac coupling s h ort i f using internal dc termination network at the r x for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 19 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz rf output stage t he r f output buffer is a cm l output stage with 50 ? impedance (single-ended) and adjustable power. i n parallel mode (the pm o de_ s e l pin = 1), it is at max gain (~ +3 d b m single-ended), whereas under s p i control, the gain can be lowered in ~3 d b steps down to -9 d b m single-ended. s ee i nterface values for more information. figure 37. output stage serial port interface (spi) control can be controlled via s p i or parallel port control (for more information on parallel control see parallel port control ). s p i control offers more fexibility. external pin pm o de- s e l = 1 confgures the for parallel port operation, while pm o de- s e l = 0 will enable the s p i control of. t he s p i control is required in order to re-confgure the input bias network from its default state ( parallel port control ), to adjust the output power control on the r f/cm l buffer, and to individually enable arbitrary l vpec l outputs. operational modes s erial port i nterface features: a. compatibility with general serial port protocols that use a shift and strobe approach to communication. b. compatible with hmc multi-chip solutions, useful to address multiple chips of various types from a single serial port bus. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 20 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz serial port write operation table 7. spi open mode - write timing characteristics parameter conditions min. t y p. max. units t 1 t2 t3 t4 t5 t 6 sdi setup time sdi hold time sen low duration sen high duration sclk 9 r ising edge to sen rising edge s erial port clock speed sen to sclk r ecovery t ime 3 3 10 10 10 dc 10 50 ns ns ns ns ns mhz ns a typical w rit e cycle is shown in figure 38 . a. t he master (host) places 9 bit data, d8:d0, m sb frst, on s d i on the frst 9 falling edges of s c lk . b. t he slave () shifts in data on s d i on the frst 9 rising edges of s c lk c. master places 4 bit register address to be written to, r3:r0, m sb frst, on the next 4 falling edges of s c lk (10 -13) d. s lave shifts the register address bits on the next 4 rising edges of s c lk (10-13). e. master places 3 bit chip address, a2:a0, m sb frst, on the next 3 falling edges of s c lk (14-16). f. s lave shifts the chip address bits on the 3 rising edges of s c lk (14-16). g. master asserts s e n after the 16th rising edge of s c lk . h. s lave registers the s d i data on the rising edge of s e n . figure 38. s p i t iming diagram, write o peration serial port read operation i n order ensure correct read operation a pull-down resistor to ground (~1-2k o hm) is recommended on the s erial data o ut line from the part. a typical r ead cycle is shown in figure 39 . i n general, s d o line is always active during the w rit e cycle. s d o will contain the data from the addresses pointed to by r eg00h . i f r eg00h is not changed, the same data will always be present on the s d o . i f it is desired to r ead from a specifc address, it is necessary in the frst s p i cycle to write the desired address to r eg00h , then in the next s p i cycle the desired data will be available on the s d o . an example of the two cycle procedure to read from any random address is as follows: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 21 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz t he master (host), on the frst 9 falling edges of s c lk places 9 bit data, d8:d0, m sb frst, on s d i as shown in figure 39 . d8:d0 should be set to zero. d3:d0 = address of the register to be r ead on the next cycle. a. t he slave () shifts in data on s d i on the frst 9 rising edges of s c lk b. master places 4 bit register address , r3:r0, ( the address the w rit e add r e ss register), m sb frst, on the next 4 falling edges of s c lk (10-13). r3:r0=0000. c. s lave shifts the register bits on the next 4 rising edges of s c lk (10-13). d. master places 3 bit chip address, a2:a0, m sb frst, on the next 3 falling edges of s c lk (14-16). e. s lave shifts the chip address bits on the next 3 rising edges of s c lk (14-16). f. master asserts s e n after the 16th rising edge of s c lk . g. s lave registers the s d i data on the rising edge of s e n . h. master clears s e n to complete the address transfer of the two part r ead cycle. i. i f we do not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on s d i to r egister zero on the r ead back part of the cycle. j. master places the same s d i data as the previous cycle on the next 16 falling edges of s c lk . k. s lave () shifts the s d i data on the next 16 rising edges of s c lk . l. s lave places the desired data (i.e. data from address in r eg00h [3:0]) on s d o on the next 16 rising edges of s c lk . m. master asserts s e n after the 16th rising edge of s c lk to complete the cycle. n ote that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the s d o output to prevent a possible bus contention issue. table 8. spi open mode - read timing characteristics parameter conditions min. t y p. max. units t 1 t2 t3 t4 t5 t6 t7 sdi setup time sdi hold time sen low duration sen high duration sclk r ising edge to sdo time sen to sclk r ecovery t ime sclk 16 r ising edge to sen rising edge 3 3 10 10 10 10 8.2+0.2ns/pf ns ns ns ns ns ns ns for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 22 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz figure 39. spi diagram, read operation 2- cycles for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 23 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz register map table 9. reg00h id register (read only) b it n ame width default description [3:0] r ead control 4 (write o nly) [4] s oft r eset [4:0] chip i d ( r ead o nly) table 10. reg01h master enable b it n ame width default description [0] master chip enable 1 1 table 11. reg02h individual enables b it n ame width default description [0] en1 1 1 enable b uffer 1 [1] en2 1 1 enable b uffer 2 [2] en3 1 1 enable b uffer 3 [3] en4 1 1 enable b uffer 4 [4] en5 1 1 enable b uffer 5 [5] en6 1 1 enable b uffer 6 [6] en7 1 1 enable b uffer 7 [7] en8 1 1 enable b uffer 8 table 12. reg03h rx buffer confguration b it n ame width default description [0] 1 0 r eserved 0 [1] dc i nternal 1 1 u se internal dc bias string [2] dc l vpec l 1 0 u se internal l vpec l r x termination [3] zin 50 1 1 i nput termination select 1 - 50 ? single-ended, 100 ? differential 0- 150 ? single-ended, 300 ? differential [4] rf bu f x or 1 0 t oggle (x or with r f bu fe n pin) the internal r f b uffer on/off [8:5] 4 0 r eserved 0 table 13. reg04h gain select b it n ame width default description [2:0] r f b uffer gain 3 7 0: disabled 1: -9 d b m single-ended 2: -6 d b m single-ended 3: -3 d b m single-ended 4: 0 d b m single-ended >4: 3 d b m single-ended for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 24 hmc987lp5e v01.0512 low noise 1:9 fanout buffer dc - 8 ghz table 14. reg05h biases b it n ame width default description [1:0] r eserved 2 2 r eserved - 2 [3:2] r eserved 2 2 r eserved - 2 [5:4] r eserved 2 3 r eserved - 3 [8:6] r eserved 3 0 r eserved - 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com

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